The present invention relates to a memory control circuit, and is employed suitably for control of a nonvolatile memory configured with a plurality of banks, for example.
In a memory control circuit in related art which supplies a power to all memories, the problem is that the power consumption of the memory becomes large, since the power is equally supplied even to a memory which is not accessed. In order to cope with such a problem, a memory control circuit is developed in which a memory is divided into banks and the memory control circuit suppresses supply of the power to a memory bank which is not accessed.
For example, in a memory apparatus disclosed by Published Japanese Unexamined Patent Application No. Sho 63 (1988)-026892 (Patent Literature 1), a power supply current is supplied to a first and a second memory bank from a power supply current control circuit. The power supply current control circuit supplies a power supply current to both the first and the second memory bank, when a signal received from a control panel is a normal mode, and supplies a power supply current only to the first memory bank, when the signal received from the control panel is a low power mode.
In a memory controller disclosed by Published Japanese Unexamined Patent Application No. Hei 07 (1995)-105686 (Patent Literature 2), under the control of a power supply control circuit, a main power from a main power supply circuit is supplied only to a memory bank corresponding to a memory address actually accessed for an instruction fetch, and a memory address predicted to be accessed in the near future. A backup power from a backup power supply circuit is supplied to other memory banks which are not accessed. Here, the memory address predicted to be accessed in the near future is calculated by adding a prescribed address value increment to the current access address.
In a micro-processor disclosed by Published Japanese Unexamined Patent Application No. 2010-15375 (Patent Literature 3), a memory unit has a normal mode and a standby mode with less power consumption than the normal mode, as an operation mode. A memory control circuit detects a branch instruction among the instructions which a CPU has fetched from the memory unit, and changes the operation mode of the memory unit corresponding to the detection result.